AMCC Proprietary 83
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
Sequential line fills can limit DCU performance. Line fills occur when a load/store or dcbt instruction misses in the
cache, and can be pipelined on the PLB interface such that up to two requests can be accepted before stalling
subsequent requests. The subsequent operations will wait in the DCU until the first line fill completes. The line fills
must complete in the order that they are accepted.
Sequential line flushes from the DCU to main memory also limit DCU performance. Flushes occur when a line fill
replaces a valid line that is marked dirty (modified), or when a dcbf instruction flushes a specific line. If two flushes
are pending, the DCU stalls any new data cache operations until the first flush finishes and the second flush
begins.
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