UM0306 Universal synchronous asynchronous receiver transmitter (USART)
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Bit 9
PS: Parity Selection.
This bit selects the odd or even parity when the parity generation/detection is
enabled (PCE bit set). It is set and cleared by software. The parity will be
selected after the current byte.
0: Even parity
1: Odd parity
Bit 8
PEIE: PE Interrupt Enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An USART interrupt is generated whenever PE=1 in the USART_SR register
Bit 7
TXEIE: TXE Interrupt Enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An USART interrupt is generated whenever TXE=1 in the USART_SR register
Bit 6
TCIE: Transmission Complete Interrupt Enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An USART interrupt is generated whenever TC=1 in the USART_SR register
Bit 5
RXNEIE: RXNE Interrupt Enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An USART interrupt is generated whenever ORE=1 or RXNE=1 in the
USART_SR register
Bit 4
IDLEIE: IDLE Interrupt Enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An USART interrupt is generated whenever IDLE=1 in the USART_SR register
Bit 3
TE: Transmitter Enable.
This bit enables the transmitter. It is set and cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
Notes:
1: During transmission, a “0” pulse on the TE bit (“0” followed by “1”) sends a
preamble (idle line) after the current word, except in smartcard mode.
2: When TE is set there is a 1 bit-time delay before the transmission starts.
Bit 2
RE: Receiver Enable.
This bit enables the receiver. It is set and cleared by software.
0: Receiver is disabled
1: Receiver is enabled and begins searching for a start bit
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