AMCC Proprietary 172
Revision 1.02 - September 10, 2007
PPC405 Processor
andi.
AND Immediate
Preliminary User’s Manual
andi.
AND Immediate
(RA) ← (RS) ∧ (
16
0 || IM)
The IM field is extended to 32 bits by concatenating 16 0-bits on its left. The contents of register RS is ANDed with
the extended IM field; the result is placed into register RA.
Registers Altered
•RA
• CR[CR0]
LT, GT, EQ, SO
Programming Note
The andi. instruction can test whether any of the 16 least-significant bits in a GPR are 1-bits.
andi. is one of three instructions that implicitly update CR[CR0] without having an Rc field. The other instructions
are addic. and andis..
Architecture Note
This instruction is part of the PowerPC User Instruction Set Architecture.
andi. RA, RS, IM
28 RS RA IM
0 6 11 16 31
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