AMCC Proprietary 173
Revision 1.02 - September 10, 2007
PPC405 Processor
andis.
AND Immediate Shifted
Preliminary User’s Manual
andis.
AND Immediate Shifted
(RA) ← (RS) ∧ (IM ||
16
0)
The IM field is extended to 32 bits by concatenating 16 0-bits on its right. The contents of register RS are ANDed
with the extended IM field; the result is placed into register RA.
Registers Altered
•RA
• CR[CR0]
LT, GT, EQ, SO
Programming Note
The andis. instruction can test whether any of the 16 most-significant bits in a GPR are 1-bits.
andis. is one of three instructions that implicitly update CR[CR0] without having an Rc field. The other instructions
are addic. and andi..
Architecture Note
This instruction is part of the PowerPC User Instruction Set Architecture.
andis. RA, RS, IM
29 RS RA IM
0 6 11 16 31
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