AMCC PPC405 - Page 174

AMCC Proprietary 174
Revision 1.02 - September 10, 2007
PPC405 Processor
b
Branch
Preliminary User’s Manual
b
Branch
If AA = 1 then
LI
← target
6:29
NIA ← EXTS(LI ||
2
0)
else
LI
← (target – CIA)
6:29
NIA ← CIA + EXTS(LI ||
2
0)
if LK = 1 then
(LR)
← CIA + 4
PC
← NIA
The next instruction address (NIA) is the effective address of the branch. The NIA is formed by adding a displace-
ment to a base address. The displacement is obtained by concatenating two 0-bits to the right of the LI field and
sign-extending the result to 32 bits.
If the AA field contains 0, the base address is the address of the branch instruction, which is also the current
instruction address (CIA). If the AA field contains 1, the base address is 0.
Program flow is transferred to the NIA.
If the LK field contains 1, then (CIA + 4) is placed into the LR.
Registers Altered
• LR if LK contains 1
Architecture Note
This instruction is part of the PowerPC User Instruction Set Architecture.
b target AA=0, LK=0
ba target AA=1, LK=0
bl target AA=0, LK=1
bla target AA=1, LK=1
18 LI AA LK
06 30 31