AMCC PPC405 - Page 175

AMCC Proprietary 175
Revision 1.02 - September 10, 2007
PPC405 Processor
bc
Branch Conditional
Preliminary User’s Manual
bc
Branch Conditional
if BO
2
= 0 then
CTR
← CTR – 1
if (BO
2
= 1 ∨ ((CTR = 0) = BO
3
)) ∧ (BO
0
=1∨ (CR
BI
= BO
1
)) then
if AA = 1 then
BD
← target
16:29
NIA ← EXTS(BD ||
2
0)
else
BD
← (target – CIA)
16:29
NIA ← CIA + EXTS(BD ||
2
0)
else
NIA
← CIA + 4
if LK = 1 then
(LR)
← CIA + 4
PC
← NIA
If bit 2 of the BO field contains 0, the CTR decrements.
The BI field specifies a bit in the CR to be used as the condition of the branch.
The next instruction address (NIA) is the effective address of the branch. The NIA is formed by adding a displace-
ment to a base address. The displacement is obtained by concatenating two 0-bits to the right of the BD field and
sign-extending the result to 32 bits.
If the AA field contains 0, the base address is the address of the branch instruction, which is also the current
instruction address (CIA). If the AA field contains 1, the base address is 0.
The BO field controls options that determine when program flow is transferred to the NIA. The BO field also
controls branch prediction, a performance-improvement feature. See Branch Prediction on page 52 for a complete
discussion.
If the LK field contains 1, then (CIA + 4) is placed into the LR.
Registers Altered
•CTR if BO
2
contains 0
• LR if LK contains 1
bc BO, BI, target AA=0, LK= 0
bca BO, BI, target AA =1, LK=0
bcl BO, BI, target AA= 0, LK=1
bcla BO, BI, target AA =1, LK=1
16 BO BI BD AA LK
0 6 11 16 30 31