AMCC Proprietary 203
Revision 1.02 - September 10, 2007
PPC405 Processor
dcbf
Data Cache Block Flush
Preliminary User’s Manual
dcbf
Data Cache Block Flush
EA ← (RA|0) + (RB)
DCBF(EA)
An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
The base address is 0 if the RA field is 0 and is the contents of register RA otherwise.
If the data block corresponding to the EA is in the data cache and marked as modified (stored into), the data block
is copied back to main storage and then marked invalid in the data cache. If the data block is not marked as modi-
fied, it is simply marked invalid in the data cache. The operation is performed whether or not the EA is marked as
cacheable.
If the data block at the EA is not in the data cache, no operation is performed.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
•None
Invalid Instruction Forms
• Reserved fields
Exceptions
This instruction is considered a “load” with respect to data storage exceptions. See Data Storage Interrupt on
page 120.
This instruction is considered a “store” with respect to data address compare (DAC) debug exceptions. See Debug
Interrupt on page 128.
Architecture Note
This instruction is part of the PowerPC Embedded Virtual Environment.
dcbf RA, RB
31
RA RB 86
0 6 11 16 21 31
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