AMCC Proprietary 204
Revision 1.02 - September 10, 2007
PPC405 Processor
dcbi
Data Cache Block Invalidate
Preliminary User’s Manual
dcbi
Data Cache Block Invalidate
EA ← (RA|0) + (RB)
DCBI(EA)
An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
The base address is 0 if the RA field is 0 and is the contents of register RA otherwise.
If the data block at the EA is in the data cache, the data block is marked invalid, regardless of whether or not the
EA is marked as cacheable. If modified data existed in the data block prior to the operation of this instruction, that
data is lost.
If the data block at the EA is not in the data cache, no operation is performed.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
•None
Invalid Instruction Forms
• Reserved fields
Programming Notes
Execution of this instruction is privileged.
Exceptions
This instruction is considered a “store” with respect to data storage exceptions. See Data Storage Interrupt on
page 120.
This instruction is considered a “store” with respect to data address compare (DAC) debug exceptions. See Debug
Interrupt on page 128.
Architecture Note
This instruction is part of the PowerPC Embedded Operating Environment.
dcbi RA, RB
31
RA RB 470
0 6 11 16 21 31
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