AMCC Proprietary 215
Revision 1.02 - September 10, 2007
PPC405 Processor
eieio
Enforce In Order Execution of I/O
Preliminary User’s Manual
eieio
Enforce In Order Execution of I/O
The eieio instruction ensures that all loads and stores preceding eieio complete with respect to main storage
before any loads and stores following eieio access main storage.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
•None
Invalid Instruction Forms
• Reserved fields
Programming Note
Architecturally, eieio orders storage access, not instruction completion. Therefore, non-storage operations after
eieio could complete before storage operations that were before eieio. The sync instruction guarantees ordering
of both instruction completion and storage access. For the PPC405, the eieio instruction is implemented to behave
as a sync instruction.
To write code that is portable between various PowerPC implementations, programmers should use the mnemonic
that corresponds to the desired behavior.
Architecture Note
This instruction is part of the PowerPC Embedded Virtual Environment.
eieio
31
854
0 6 21 31
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