AMCC Proprietary 214
Revision 1.02 - September 10, 2007
PPC405 Processor
divwu
Divide Word Unsigned
Preliminary User’s Manual
divwu
Divide Word Unsigned
(RT) ← (RA) ÷ (RB)
The contents of register RA are divided by the contents of register RB. The quotient is placed into register RT.
The dividend and the divisor are interpreted as unsigned integers. The quotient is the unique unsigned integer that
satisfies:
dividend = (quotient × divisor) + remainder
If an attempt is made to perform (n ÷ 0), the contents of register RT are undefined; if the Rc also contains 1, the
contents of CR[CR0]
LT, GT, EQ
are also undefined. The invalid division operation also sets XER[OV, SO] to 1 if the
OE field contains 1.
Registers Altered
•RT
• CR[CR0]
LT, GT, EQ, SO
if Rc contains 1
• XER[OV, SO] if OE contains 1
Programming Note
The 32-bit remainder can be calculated using the following sequence of instructions
divwu RT,RA,RB # RT = quotient
mullw RT,RT,RB # RT = quotient × divisor
subf RT,RT,RA # RT = remainder
This sequence does not calculate the correct result if the divisor is zero.
Architecture Note
This instruction is part of the PowerPC User Instruction Set Architecture.
divwu RT, RA, RB OE=0, Rc=0
divwu. RT, RA, RB OE=0, Rc=1
divwuo RT, RA, RB OE=1, Rc=0
divwuo. RT, RA, RB OE=1, Rc=1
31 RT RA RB OE 459 Rc
0 6 11 16 21 22 31
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