AMCC Proprietary 213
Revision 1.02 - September 10, 2007
PPC405 Processor
divw
Divide Word
Preliminary User’s Manual
divw
Divide Word
(RT) ← (RA) ÷ (RB)
The contents of register RA are divided by the contents of register RB. The quotient is placed into register RT.
Both the dividend and the divisor are interpreted as signed integers. The quotient is the unique signed integer that
satisfies:
dividend = (quotient × divisor) + remainder
where the remainder has the same sign as the dividend and its magnitude is less than that of the divisor.
If an attempt is made to perform (0x8000 0000 ÷ –1) or (
n ÷ 0), the contents of register RT are undefined; if the Rc
field also contains 1, the contents of CR[CR0]
LT, GT, EQ
are undefined. Either invalid division operation sets
XER[OV, SO] to 1 if the OE field contains 1.
Registers Altered
•RT
• CR[CR0]
LT, GT, EQ, SO
if Rc contains 1
• XER[OV, SO] if OE contains 1
Programming Note
The 32-bit remainder can be calculated using the following sequence of instructions:
divw RT,RA,RB # RT = quotient
mullw RT,RT,RB # RT = quotient × divisor
subf RT,RT,RA # RT = remainder
The sequence does not calculate correct results for the invalid divide operations.
Architecture Note
This instruction is part of the PowerPC User Instruction Set Architecture.
divw RT, RA, RB OE=0, Rc=0
divw. RT, RA, RB OE=0, Rc=1
divwo RT, RA, RB OE=1, Rc=0
divwo. RT, RA, RB OE=1, Rc=1
31 RT RA RB OE 491 Rc
0 6 11 16 21 22 31
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