AMCC Proprietary 212
Revision 1.02 - September 10, 2007
PPC405 Processor
dcread
Data Cache Read
Preliminary User’s Manual
Exceptions
If EA is not word-aligned, an alignment exception occurs.
This instruction is considered a “load” with respect to data storage exceptions, but cannot cause a data storage
exception. See Access Protection for Cache Control Instructions on page 104.
The execution of an dcread instruction can cause a data TLB miss exception, at the specified EA, regardless of
the non-specific intent of that effective address.
This instruction is considered a “load” with respect to data address compare (DAC) debug exceptions. See Debug
Interrupt on page 128.
Architecture Note
This instruction is implementation-specific and may not be portable to other implementations.
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