AMCC Proprietary 219
Revision 1.02 - September 10, 2007
PPC405 Processor
icbi
Instruction Cache Block Invalidate
Preliminary User’s Manual
0.Instruction Seticbi
Instructio n Cache Block Inva lidate
EA ← (RA|0) + (RB)
ICBI(EA)
An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
The base address is 0 if the RA field is 0 and is the contents of register RA otherwise.
If the instruction block at the EA is in the instruction cache, the cache block is marked invalid.
If the instruction block at the EA is not in the instruction cache, no additional operation is performed.
The operation specified by this instruction is performed whether or not the EA is marked as cacheable in the ICCR.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
•None
Invalid Instruction Forms
• Reserved fields
Programming Note
Instruction cache operations use MSR[DR], not MSR[IR], to determine translation of their operands.
When data translation is disabled, cachability for the EA of the operand of instruction cache operations is deter-
mined by the ICCR, not the DCCR.
Exceptions
Instruction storage exceptions and instruction-side TLB miss exceptions are associated with instruction fetching,
not with instruction execution. Exceptions that occur during the execution of instruction cache operations cause
data-side exceptions (data storage exceptions and data TLB miss exceptions).
This instruction is considered a “load” with respect to data storage exceptions. See Debug Interrupt on page 128.
This instruction is considered a “load” with respect to data address compare (DAC) debug exceptions.
Architecture Note
This instruction is part of the PowerPC Embedded Virtual Environment.
icbi RA, RB
31
RA RB 982
0 6 11 16 21 31
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