AMCC Proprietary 220
Revision 1.02 - September 10, 2007
PPC405 Processor
icbt
Instruction Cache Block Touch
Preliminary User’s Manual
icbt
Instructio n Cache Block Touch
EA← (RA|0) + (RB)
ICBT(EA)
An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
The base address is 0 if the RA field is 0 and is the contents of register RA otherwise.
If the instruction block at the EA is not in the instruction cache, and is marked as cacheable, the instruction block is
loaded into the instruction cache.
If the instruction block at the EA is in the instruction cache, or if the EA is marked as non cacheable, no operation is
performed.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
•None
Invalid Instruction Forms
• Reserved fields
Programming Notes
This instruction allows a program to begin a cache block fetch from main storage before the program needs the
instruction. The program can later branch to the instruction address and fetch the instruction from the cache
without incurring the latency of a cache miss.
Instruction cache operations use MSR[DR], not MSR[IR], to determine translation of their operands. When data
translation is disabled, cachability for the effective address of the operand of instruction cache operations is deter-
mined by the ICCR, not the DCCR.
Exceptions
Instruction storage exceptions and instruction-side TLB miss exceptions are associated with instruction fetching,
not with instruction execution. Exceptions occurring during execution of instruction cache operations cause data
storage and data TLB miss exceptions.
If the execution of an icbt instruction would cause a data TLB miss exception, no operation is performed and no
exception occurs.
This instruction is considered a “load” with respect to protection exceptions, but cannot cause data storage excep-
tions. This instruction is also considered a “load” with respect to data address compare (DAC) debug exceptions.
Architecture Note
This instruction is part of the PowerPC Embedded Operating Environment.
icbt RA, RB
31
RA RB 262
0 6 11 16 21 31
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