AMCC Proprietary 227
Revision 1.02 - September 10, 2007
PPC405 Processor
lbzux
Load Byte and Zero with Update Indexed
Preliminary User’s Manual
lbzux
Load Byte and Zero with Update Indexed
EA ← (RA|0) + (RB)
(RA)
← EA
(RT)
←
24
0 || MS(EA,1)
An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
The base address is 0 if the RA field is 0 and is the contents of register RA otherwise. The EA is placed into
register RA.
The byte at the EA is extended to 32 bits by concatenating 24 0-bits to its left. The result is placed into register RT.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
•RA
•RT
Invalid Instruction Forms
• Reserved fields
•RA=RT
•RA=0
Architecture Note
This instruction is part of the PowerPC User Instruction Set Architecture.
lbzux RT, RA, RB
31 RT RA RB 119
0 6 11 16 21 31
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