AMCC Proprietary 239
Revision 1.02 - September 10, 2007
PPC405 Processor
lswi
Load String Word Immediate
Preliminary User’s Manual
lswi
Load String Word Immedia te
EA ← (RA|0)
if NB = 0 then
CNT
← 32
else
CNT
← NB
n
← CNT
R
FINAL
← ((RT + CEIL(CNT/4) – 1) % 32)
r
← RT – 1
i
← 0
dowhilen>0
if i = 0 then
r
← r+1
if r = 32 then
r
← 0
if ((r
≠ RA) ∨ (r = R
FINAL
)) then
(GPR(r))
← 0
if ((r
≠ RA) ∨ (r = R
FINAL
)) then
(GPR(r)
i:i+7
) ← MS(EA,1)
i
← i+8
if i = 32 then
i
← 0
EA
← EA + 1
n
← n–1
An effective address (EA) is determined by the RA field. If the RA field contains 0, the EA is 0. Otherwise, the EA is
the contents of register RA.
The NB field specifies the byte count CNT. If the NB field contains 0, the byte count is CNT = 32. Otherwise, the
byte count is CNT = NB.
A series of CNT consecutive bytes in main storage, starting at the EA, are loaded into CEIL(CNT/4) consecutive
GPRs, four bytes per GPR, until the byte count is exhausted. Bytes are loaded into GPRs; the byte at the lowest
address is loaded into the most significant byte. Bits to the right of the last byte loaded into the last GPR are set to
0.
The set of loaded GPRs starts at register RT, continues consecutively through GPR(31), and wraps to register 0,
loading until the byte count is exhausted, which occurs in register R
FINAL
. Register RA is not altered (unless
RA = R
FINAL
, an invalid form of this instruction). Bytes which would have been loaded into register RA are
discarded.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
• RT and subsequent GPRs as described above.
l
swi RT, RA, NB
31 RT RA NB 597
0 6 11 16 21 31
To Next Page
Loading...