AMCC Proprietary 242
Revision 1.02 - September 10, 2007
PPC405 Processor
lswx
Load String Word Indexed
Preliminary User’s Manual
•RA=RT=0
Programming Note
If XER[TBC] = 0, the contents of register RT are unchanged and lswx is treated as a no-op.
The PowerPC Architecture states that, if XER[TBC] = 0 and if the EA is such that a precise data exception would
normally occur (if not for the zero length), lswx is treated as a no-op and the precise exception will not occur. Data
storage exceptions and alignment exceptions are examples of precise data exceptions.
However, the PowerPC Architecture makes no statement regarding imprecise exceptions related to lswx with
XER[TBC] = 0. The PPC405 generates an imprecise exception (machine check) on this instruction when all of the
following conditions are true:
• The instruction passes all protection bounds checking
• The address is cacheable
• The address is passed to the data cache
• The address misses in the data cache (resulting in a line fill request)
• The address encounters some form of bus error
Architecture Note
This instruction is part of the PowerPC User Instruction Set Architecture.
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