AMCC Proprietary 243
Revision 1.02 - September 10, 2007
PPC405 Processor
lwarx
Load Word and Reserve Indexed
Preliminary User’s Manual
lwarx
Load Word and Reserve Indexe d
EA ← (RA|0) + (RB)
RESERVE
← 1
(RT)
← MS(EA,4)
An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
The base address is 0 if the RA field is 0 and is the contents of register RA otherwise.
The word at the EA is placed into register RT.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Execution of the lwarx instruction sets the reservation bit.
Registers Altered
•RT
Invalid Instruction Forms
• Reserved fields
Programming Note
lwarx and the stwcx. instruction should paired in a loop, as shown in the following example, to create the effect of
an atomic operation to a memory area used as a semaphore between asynchronous processes. Only lwarx can
set the reservation bit to 1. stwcx. sets the reservation bit to 0 upon its completion, whether or not stwcx. sent
(RS) to memory. CR[CR0]
EQ
must be examined to determine whether (RS) was sent to memory.
loop: lwarx # read the semaphore from memory; set reservation
“alter” # change the semaphore bits in register as required
stwcx. # attempt to store semaphore; reset reservation
bne loop # an asynchronous process has intervened; try again
If the asynchronous process in the code example had paired lwarx with a store other than stwcx., the reservation
bit would not have been cleared in the asynchronous process, and the code example would have overwritten the
semaphore.
Exceptions
An alignment exception occurs if the EA is not word-aligned.
Architecture Note
This instruction is part of the PowerPC User Instruction Set Architecture.
l
warx RT, RA, RB
31 RT RA RB 20
0 6 11 16 21 31
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