AMCC Proprietary 244
Revision 1.02 - September 10, 2007
PPC405 Processor
lwbrx
Load Word Byte-Reverse Indexed
Preliminary User’s Manual
lwbrx
Load Word Byte-Reverse Indexed
EA ← (RA|0) + (RB)
(RT)
← MS(EA+3,1) || MS(EA+2,1) || MS(EA+1,1) || MS(EA,1)
An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
The base address is 0 if the RA field is 0 and is the contents of register RA otherwise.
The word at the EA is byte-reversed: the least significant byte becomes the most significant byte, the next least
significant byte becomes the next most significant byte, and so on. The resulting word is placed into register RT.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
•RT
Invalid Instruction Forms
• Reserved fields
Architecture Note
This instruction is part of the PowerPC User Instruction Set Architecture.
lwbrx RT, RA, RB
31 RT RA RB 534
0 6 11 16 21 31
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