AMCC Proprietary 247
Revision 1.02 - September 10, 2007
PPC405 Processor
lwzux
Load Word and Zero with Update Indexed
Preliminary User’s Manual
lwzux
Load Word and Zero with Update Indexed
EA ← (RA) + (RB)
(RA)
← EA
(RT)
← MS(EA,4)
An effective address (EA) is formed by adding an index to the base address in register RA. The index is the
contents of register RB. The EA is placed into register RA.
The word at the EA is placed into register RT.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
•RA
•RT
Invalid Instruction Forms
• Reserved fields
•RA=RT
•RA=0
Architecture Note
This instruction is part of the PowerPC User Instruction Set Architecture.
lwzux RT, RA, RB
31 RT RA RB 55
0 6 11 16 21 31
To Next Page
Loading...