AMCC Proprietary 303
Revision 1.02 - September 10, 2007
PPC405 Processor
sc
System Call
Preliminary User’s Manual
sc
System Call
(SRR1) ← (MSR)
(SRR0)
← (PC)
PC
← EVPR
0:15
|| 0x0C00
(MSR[WE, EE, PR, DR, IR]) ← 0
A system call exception is generated. The contents of the MSR are copied into SRR1 and (4 + address of sc
instruction) is placed into SRR0.
The program counter (PC) is then loaded with the exception vector address. The exception vector address is
calculated by concatenating the high halfword of the Exception Vector Prefix Register (EVPR) to the left of 0x0C00.
The MSR[WE, EE, PR, DR, IR] bits are set to 0.
Program execution continues at the new address in the PC.
The sc instruction is context synchronizing.
Registers Altered
• SRR0
• SRR1
• MSR[WE, EE, PR, DR, IR]
Invalid Instruction Forms
• Reserved fields
Architecture Note
This instruction is part of the PowerPC User Instruction Set Architecture.
sc
17
1
06 30 31
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