AMCC Proprietary 316
Revision 1.02 - September 10, 2007
PPC405 Processor
sthx
Store Halfword Indexed
Preliminary User’s Manual
sthx
Store Halfword Indexed
EA ← (RA|0) + (RB)
MS(EA, 2)
← (RS)
16:31
An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
The base address is 0 when the RA field is 0, and is the contents of register RA otherwise.
The least significant halfword of register RS is stored into the halfword at the EA.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
•None
Invalid Instruction Forms
• Reserved fields
Architecture Note
This instruction is part of the PowerPC User Instruction Set Architecture.
sthx RS, RA, RB
31 RS RA RB 407
0 6 11 16 21 31
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