AMCC Proprietary 315
Revision 1.02 - September 10, 2007
PPC405 Processor
sthux
Store Halfword with Update Indexed
Preliminary User’s Manual
sthux
Store Halfword with Update Indexed
EA ← (RA) + (RB)
MS(EA, 2)
← (RS)
16:31
(RA) ← EA
An effective address (EA) is formed by adding an index to the base address in register RA. The index is the
contents of register RB. The EA is placed into register RA.
The least significant halfword of register RS is stored into the halfword at the EA.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
•RA
Invalid Instruction Forms
• Reserved fields
•RA=0
Architecture Note
This instruction is part of the PowerPC User Instruction Set Architecture.
sthux RS, RA, RB
31 RS RA RB 439
0 6 11 16 21 31
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