AMCC PPC405 - Page 444

444 AMCC Confidential and Proprietary
PPC405 Processor
Revision 1.02 - September 10, 2007
Preliminary User’s Manual
srawi 306
srawi. 306
srw 307
srw.
307
stb 308
stbu
309
stbux 310
stbx 311
sth
312
sthbrx 313
sthu 314
sthux
315
sthx 316
stmw 317
stswi
318
stswx 319
stw 321
stwbrx
322
stwcx. 323
stwu 324
stwux
325
stwx 326
subf 327
subf.
327
subfc 328
subfc. 328
subfco
328
subfco. 328
subfe 329
subfe.
329
subfeo 329
subfeo. 329
subfic
330
subfme 331
subfme. 331
subfmeo
331
subfmeo.
331
subfo 327
subfo.
327
subfze
332
subfze. 332
subfzeo
332
subfzeo.
332
sync
333
tlbia
334
tlbre
335
tlbsx
337
tlbsx.
337
tlbsync
338
tlbwe
339
tw
341
twi
344
wrtee
347
wrteei
348
xor
349
xori
350
instruction fields
357
instruction formats 357
diagrams
359
instruction forms
357, 359
instruction processing 49
instruction storage interrupts
register settings
122
instruction summary 357
by category
395
instruction timing 430
instruction timings 431
branches and cr logicals
432
general rules 431
instruction cache misses 435
loads and stores
435
strings 434
instructions 157
alphabetical, including extended mnemonics
362
arithmetic and logical 420
branch 424
cache
DAC debug events
152
cache control 427
comparison
425
condition register logical 424
extended mnemonics 402
format diagrams
359
formats 357
forms 357, 359
interrupt control
427
list 160
opcodes 388
portability
157
privileged 400
processor management 429
pseudocode
158
registers 160
rotate and shift 426
specific to PowerPC Embedded Controllers
398
storage reference
417
TLB management 428
interrrupt
priority
111
interrupt
critical
112
data storage
120
debug
128
external
122
handling
109
input
118
instruction storage
121
machine check
118
non-critical
112
registers
114
TLB miss
127
interrupts
alignment
register settings
123
data storage
register settings
121
defined 109
DTLB miss
100