AMCC PPC405 - Page 445

AMCC Confidential and Proprietary 445
Revision 1.02 - September 10, 2007
Preliminary User’s Manual
PPC405 Processor
external
register settings 122
FIT, causes 125
FIT, register settings
126
handling priorities, illustrated 111
instruction storage
register settings
122
machine check—instruction
register settings
119
program
ESR usage 123
register settings
124
register settings during critical 118
vector offsets, illustrated 113
WDT, causes
126
WDT, register settings 126
isync 224
L
lbz 225
lbzu 226
lbzx 228
lha
229
lhau 230
lhax 232
lhbrx
233
lhz 234
lhzu 235
lhzux
236
lhzx 237
li 164
lis
167
little endien 45
lmw 238
LR
37
lswi
239
lswx 241
lwarx
243
lwz 245
lwzu
246
lwzux
247
lwzx
248
M
macchw 249
macchws
250
macchwsu 251
macchwu
252
machhw
253
machhwsu
255
machhwu
256
machine check—instruction interrupts
register settings 119
maclhw
257
maclhws
258, 291
maclhwu
260
mcrf 261
mcrxr 262
memory management
91
address translation 91
overview
91
mfcr 263
mfdcr 264
mfmsr
265
mfspr 266
mftb 268
mftbu
268
MMU (memory management unit)
DTLB miss interrupts 100
mr
293
mr. 293
MSR 114, 353
mtcr
269
mtcrf 269
mtdcr 270
mtspr
272
mulchw 274
mulchwu 275
mulhhw
276
mulhhwu 277
mulhwu 279
mulhwu.
279
mullhw 280
mullhwu 281
mulli
282
mullw 283
mullw. 283
mullwo
283
mullwo. 283
N
nand 284
nand.
284
neg 285
neg.
285
nego
285
nego.
285
nmacchw
286
nmacchws
287
nmachhw
288
nmachhws
289
nmaclhw
290
nmaclhws
291
nop
295
nor
292
nor.
292
not
292
not.
292
notation
357