AMCC PPC405 - Page 446

446 AMCC Confidential and Proprietary
PPC405 Processor
Revision 1.02 - September 10, 2007
Preliminary User’s Manual
O
on-chip memory 85
addressing
86
coherency 86
registers 88
opcodes
388
optimization
coding guidelines
430
alignment 431
boolean variables 430
branch prediction
431
dependency upon CR 431
or 293
or.
293
orc 294
orc. 294
organization, processor
23
ori 295
oris 296
overview
21
P
PID 102
PIT 131
primary opcodes
388
privileged mode
registers 34
processor
21
program interrupts
ESR usage 123
register settings
124
programming model 31
programming model, processor 26
programming note
instruction pipeline
80
PVR 39
R
real mode storage 105
register summary
353
registers
CCR0
77
CR
39
CTR
36
DAC1–DAC2
147
DBCRx
143
DBSR
145
DCCR
106
DCWR
106
DEAR
118
device control
356
during debug exceptions
128
DVC1–DVC2
147
ESR
116
EVPR 116
GPR0-GPR31 35
IAC1–IAC4 147
ICCR
107
ICDBR 80
LR
37
MSR 114
PID 102
PIT
131
PVR 39
SGR 107
SLER
107
SPRG0-SPRG7 39
SSR0-SSR1 115
SSR2-SSR3
115
SU0R 107
supervisor, illustrated 34
TBH
130
TBL 130
TCR 135
TSR
135
user, illustrated 34
USPRG0 39
XER
37
ZPR 103
registers general 32
reservation bit
243, 323
rfci 297
rfi 298
rlwimi
299
rlwimi. 299
rlwinm 300
rlwinm.
300
rlwnm 302
rlwnm. 302
rotlw
302
rotlw.
302
rotlwi 301
rotlwi.
301
rotrwi
301
rotrwi. 301
rxtended mnemonics
bnectr
182
S
sc 303
secondary opcodes
388
SGR
107
SLER
107
slw
304
slw.
304
slwi
301
slwi.
301
speculative access
53
SPR
35, 354
SPRG0-SPRG7
39
SPRs (special purpose registers)