UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 13 of 368
NXP Semiconductors
UM10375
Chapter 3: LPC13xx System configuration
3.4 Clocking and power control
See Figure 3 for an overview of the LPC13xx Clock Generation Unit (CGU).
The LPC131x include three independent oscillators. These are the system oscillator, the
Internal RC oscillator (IRC), and the Watchdog oscillator. Each oscillator can be used for
more than one purpose as required in a particular application.
Following reset, the LPC131x will operate from the Internal RC oscillator until switched by
software. This allows systems to operate without any external crystal and the bootloader
code to operate at a known frequency.
The SYSAHBCLKCTRL register gates the system clock to the various peripherals and
memories. UART, SSP0/1, the SysTick timer, and the ARM trace clock have individual
clock dividers to derive peripheral clocks from the main clock.
The USB clock, if available, and the watchdog clock, can be derived from the oscillator
output or the main clock.
The main clock, and the clock outputs from the IRC, the system oscillator, and the
watchdog oscillator can be observed directly on the CLKOUT pin.
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