UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 310 of 368
NXP Semiconductors
UM10375
Chapter 19: LPC13xx Windowed WatchDog Timer (WWDT)
19.7.6 Watchdog Timer Window register
The WDWINDOW register determines the highest WDTV value allowed when a watchdog
feed is performed. If a feed valid sequence completes prior to WDTV reaching the value in
WDWINDOW, a watchdog event will occur.
WDWINDOW resets to the maximum possible WDTV value, so windowing is not in effect.
19.7.7 Watchdog timing examples
The following figures illustrate several aspects of Watchdog Timer operation.
Table 301: Watchdog Timer Warning Interrupt register (WDWARNINT - 0x4000 4014) bit
description
Bit Symbol Description Reset value
9:0 WARNINT Watchdog warning interrupt compare value. 0
31:10 - Reserved. Read value is undefined, only zero should be
written.
-
Table 302: Watchdog Timer Window register (WDWINDOW - 0x4000 4018) bit description
Bit Symbol Description Reset value
23:0 WINDOW Watchdog window value. 0xFF FFFF
31:24 - Reserved. Read value is undefined, only zero should be
written.
-
Fig 60. Early Watchdog Feed with Windowed Mode Enabled
125A 12581259 1257
WDCLK / 4
Watchdog
Counter
Early Feed
Event
Watchdog
Reset
Conditions:
WINDOW = 0x1200
WARNINT = 0x3FF
TC = 0x2000
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