UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 147 of 368
NXP Semiconductors
UM10375
Chapter 10: LPC13xx USB device controller
10.10.1.4 USB Device Interrupt Set register (USBDevIntSet - 0x4002 000C)
Writing one to a bit in this register sets the corresponding bit in the USBDevIntSt. Writing a
zero has no effect
USBDevIntSet is a write only register.
6 EP5_CLR USB core interrupt for physical endpoint 5.
0 = no effect.
1 = the corresponding bit in USBDevIntSt is cleared.
0
7 EP6_CLR USB core interrupt for physical endpoint 6.
0 = no effect.
1 = the corresponding bit in USBDevIntSt is cleared.
0
8 EP7_CLR USB core interrupt for physical endpoint 7.
0 = no effect.
1 = the corresponding bit in USBDevIntSt is cleared.
0
9 DEV_STAT_CLR Set when USB Bus reset, USB suspend change, or
Connect change event occurs.
0 = no effect.
1 = the corresponding bit in USBDevIntSt is cleared.
0
10 CC_EMPTY_CLR The command code register (USBCmdCode) is empty
(New command can be written).
0 = no effect.
1 = the corresponding bit in USBDevIntSt is cleared.
0
11 CD_FULL_CLR Command data register (USBCmdData) is full (Data
can be read now).
0 = no effect.
1 = the corresponding bit in USBDevIntSt is cleared.
0
12 RXENDPKT_CLR The current packet in the endpoint buffer is transferred
to the CPU.
0 = no effect.
1 = the corresponding bit in USBDevIntSt is cleared.
0
13 TXENDPKT_CLR The number of data bytes transferred to the endpoint
buffer equals the number of bytes programmed in the
TxPacket length register (USBTxPLen).
0 = no effect.
1 = the corresponding bit in USBDevIntSt is cleared.
0
31:14 - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
-
Table 165. USB Device Interrupt Clear register (USBDevIntClr - address 0x4002 0008) bit
description
Bit Symbol Description Reset
value
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