NXP Semiconductors LPC1311 - Reserved

UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 367 of 368
NXP Semiconductors
UM10375
Chapter 23: LPC13xx Supplementary information
18.7.1 Watchdog Mode register (WDMOD -
0x4000 0000) . . . . . . . . . . . . . . . . . . . . . . . . 301
18.7.2 Watchdog Timer Constant register (WDTC -
0x4000 4004) . . . . . . . . . . . . . . . . . . . . . . . . 302
18.7.3 Watchdog Feed register (WDFEED -
0x4000 4008). . . . . . . . . . . . . . . . . . . . . . . . 302
18.7.4 Watchdog Timer Value register (WDTV -
0x4000 400C) . . . . . . . . . . . . . . . . . . . . . . . 303
18.8 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . 303
Chapter 19: LPC13xx Windowed WatchDog Timer (WWDT)
19.1 How to read this chapter. . . . . . . . . . . . . . . . 304
19.2 Basic configuration . . . . . . . . . . . . . . . . . . . . 304
19.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
19.4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 305
19.5 General description. . . . . . . . . . . . . . . . . . . . 305
19.6 Clocking and power control . . . . . . . . . . . . . 306
19.7 Register description . . . . . . . . . . . . . . . . . . . 307
19.7.1 Watchdog Mode register . . . . . . . . . . . . . . . 307
19.7.2 Watchdog Timer Constant register . . . . . . . 308
19.7.3 Watchdog Feed register . . . . . . . . . . . . . . . 309
19.7.4 Watchdog Timer Value register . . . . . . . . . . 309
19.7.5 Watchdog Timer Warning Interrupt register 309
19.7.6 Watchdog Timer Window register . . . . . . . . 310
19.7.7 Watchdog timing examples . . . . . . . . . . . . . 310
Chapter 20: LPC13xx Analog-to-Digital Converter (ADC)
20.1 How to read this chapter. . . . . . . . . . . . . . . . 312
20.2 Basic configuration . . . . . . . . . . . . . . . . . . . . 312
20.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
20.4 Pin description. . . . . . . . . . . . . . . . . . . . . . . . 312
20.5 Clocking and power control . . . . . . . . . . . . . 313
20.6 Register description . . . . . . . . . . . . . . . . . . . 313
20.6.1 A/D Control Register (AD0CR -
0x4001 C000). . . . . . . . . . . . . . . . . . . . . . . . 314
20.6.2 A/D Global Data Register (AD0GDR -
0x4001 C004). . . . . . . . . . . . . . . . . . . . . . . . 315
20.6.3 A/D Interrupt Enable Register (AD0INTEN -
0x4001 C00C) . . . . . . . . . . . . . . . . . . . . . . . 316
20.6.4 A/D Data Registers (AD0DR0 to AD0DR7 -
0x4001 C010 to 0x4001 C02C) . . . . . . . . . . 316
20.6.5 A/D Status Register (AD0STAT -
0x4001 C030) . . . . . . . . . . . . . . . . . . . . . . . 316
20.7 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
20.7.1 Hardware-triggered conversion . . . . . . . . . . 317
20.7.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Chapter 21: LPC13xx Flash memory programming firmware
21.1 How to read this chapter. . . . . . . . . . . . . . . . 318
21.2 Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
21.2.1 Bootloader code version 5.2 notes. . . . . . . . 319
21.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
21.4 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
21.5 Memory map after any reset . . . . . . . . . . . . . 320
21.6 Flash content protection mechanism . . . . . 320
21.7 Criterion for Valid User Code . . . . . . . . . . . . 321
21.8 ISP/IAP communication protocol. . . . . . . . . 321
21.8.1 ISP command format . . . . . . . . . . . . . . . . . . 321
21.8.2 ISP response format. . . . . . . . . . . . . . . . . . . 321
21.8.3 ISP data format. . . . . . . . . . . . . . . . . . . . . . . 322
21.8.4 ISP flow control. . . . . . . . . . . . . . . . . . . . . . . 322
21.8.5 ISP command abort . . . . . . . . . . . . . . . . . . . 322
21.8.6 Interrupts during ISP. . . . . . . . . . . . . . . . . . . 322
21.8.7 Interrupts during IAP. . . . . . . . . . . . . . . . . . . 322
21.8.8 RAM used by ISP command handler . . . . . . 322
21.8.9 RAM used by IAP command handler . . . . . . 322
21.9 USB communication protocol . . . . . . . . . . . 323
21.9.1 Usage note . . . . . . . . . . . . . . . . . . . . . . . . . . 323
21.10 Boot process flowchart. . . . . . . . . . . . . . . . . 324
21.11 Sector numbers . . . . . . . . . . . . . . . . . . . . . . . 325
21.12 Code Read Protection (CRP) . . . . . . . . . . . . 325
21.12.1 ISP entry protection . . . . . . . . . . . . . . . . . . . 327
21.13 ISP commands . . . . . . . . . . . . . . . . . . . . . . . 328
21.13.1 Unlock <Unlock code>. . . . . . . . . . . . . . . . . 328
21.13.2 Set Baud Rate <Baud Rate> <stop bit>. . . . 329
21.13.3 Echo <setting>. . . . . . . . . . . . . . . . . . . . . . . 329
21.13.4 Write to RAM <start address>
<number of bytes>. . . . . . . . . . . . . . . . . . . . 329
21.13.5 Read Memory <address> <no. of bytes>. . . 330
21.13.6 Prepare sector(s) for write operation <start sector
number> <end sector number> . . . . . . . . . . 330
21.13.7 Copy RAM to flash <Flash address> <RAM
address> <no of bytes> . . . . . . . . . . . . . . . . 331
21.13.8 Go <address> <mode> . . . . . . . . . . . . . . . . 332
21.13.9 Erase sector(s) <start sector number> <end
sector number> . . . . . . . . . . . . . . . . . . . . . . 333
21.13.10 Blank check sector(s) <sector number> <end
sector number> . . . . . . . . . . . . . . . . . . . . . . 333
21.13.11 Read Part Identification number . . . . . . . . . 333
21.13.12 Read Boot code version number . . . . . . . . . 334
21.13.13 Compare <address1> <address2>
<no of bytes> . . . . . . . . . . . . . . . . . . . . . . . . 334
21.13.14 ReadUID . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
21.13.15 ISP Return Codes . . . . . . . . . . . . . . . . . . . . 335
21.14 IAP commands . . . . . . . . . . . . . . . . . . . . . . . 336
21.14.1 Prepare sector(s) for write operation . . . . . . 337
21.14.2 Copy RAM to flash. . . . . . . . . . . . . . . . . . . . 338
21.14.3 Erase Sector(s) . . . . . . . . . . . . . . . . . . . . . . 339