UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 256 of 368
NXP Semiconductors
UM10375
Chapter 14: LPC13xx SSP0/1
14.7.4 SSP Status Register
This read-only register reflects the current status of the SSP controller.
14.7.5 SSP Clock Prescale Register
This register controls the factor by which the Prescaler divides the SSP peripheral clock
SSP_PCLK to yield the prescaler clock that is, in turn, divided by the SCR factor in
SSP0CR0, to determine the bit clock.
Important: the SSP0CPSR value must be properly initialized or the SSP controller will not
be able to transmit data correctly.
In Slave mode, the SSP clock rate provided by the master must not exceed 1/12 of the
SSP peripheral clock selected in Table 26
or Table 28. The content of the SSP0CPSR
register is not relevant.
In master mode, CPSDVSR
min
= 2 or larger (even numbers only).
14.7.6 SSP Interrupt Mask Set/Clear Register
This register controls whether each of the four possible interrupt conditions in the SSP
controller are enabled. Note that ARM uses the word “masked” in the opposite sense from
classic computer terminology, in which “masked” meant “disabled”. ARM uses the word
“masked” to mean “enabled”. To avoid confusion we will not use the word “masked”.
Table 246: SSP Status Register (SSP0SR - address 0x4004 000C, SSP1SR - address
0x4005 800C) bit description
Bit Symbol Description Reset value
0 TFE Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is
empty, 0 if not.
1
1 TNF Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. 1
2 RNE Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is
empty, 1 if not.
0
3 RFF Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if
not.
0
4 BSY Busy. This bit is 0 if the SSP0 controller is idle, or 1 if it is
currently sending/receiving a frame and/or the Tx FIFO is not
empty.
0
31:5 - Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
NA
Table 247: SSP Clock Prescale Register (SSP0CPSR - address 0x4004 0010, SSP1CPSR -
address 0x4005 8010) bit description
Bit Symbol Description Reset value
7:0 CPSDVSR This even value between 2 and 254, by which SSP_PCLK is
divided to yield the prescaler output clock. Bit 0 always reads
as 0.
0
31:8 - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
NA
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