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User manual Rev. 3 — 14 June 2011 77 of 368
NXP Semiconductors
UM10375
Chapter 6: LPC13xx Interrupt controller
6.6.11 Interrupt Priority Register 0
The IPR0 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 32 priorities, where 0 is the highest priority.
6.6.12 Interrupt Priority Register 1
The IPR1 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 32 priorities, where 0 is the highest priority.
Table 78. Interrupt Priority Register 0 (IPR0 - address 0xE000 E400) bit description
Bit Symbol Description
4:0 Unimplemented These bits ignore writes, and read as 0.
7:5 IP_PIO0_0 PIO0_0 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
12:8 Unimplemented These bits ignore writes, and read as 0.
15:13 IP_PIO0_1 PIO0_1 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
20:16 Unimplemented These bits ignore writes, and read as 0.
23:21 IP_PIO0_2 PIO0_2 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
28:24 Unimplemented These bits ignore writes, and read as 0.
31:29 IP_PIO0_3 PIO0_3 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
Table 79. Interrupt Priority Register 1 (IPR1 - address 0xE000 E404) bit description
Bit Symbol Description
4:0 Unimplemented These bits ignore writes, and read as 0.
7:5 IP_PIO0_4 PIO0_4 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
12:8 Unimplemented These bits ignore writes, and read as 0.
15:13 IP_PIO0_5 PIO0_5 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
20:16 Unimplemented These bits ignore writes, and read as 0.
23:21 IP_PIO0_6 PIO0_6 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
28:24 Unimplemented These bits ignore writes, and read as 0.
31:29 IP_PIO0_7 PIO0_7 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
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