UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 11 of 368
NXP Semiconductors
UM10375
Chapter 3: LPC13xx System configuration
Input pins to the start logic
For HVQFN packages, the start logic control bits (see Table 44
to Table 51) are reserved
for port pins PIO2_1 to PIO2_11 and PIO3_0, PIO3_1, and PIO3_3.
PIO reset status registers
For HVQFN packages, the reset status bits (see Table 40
and Table 41) are reserved for
port pins PIO2_1 to PIO2_11 and PIO3_0 and PIO3_1, and PIO3_3.
Entering Deep power-down mode
Status of the IRC before entering Deep power-down mode (see Section 3.9.4.2
):
• IRC must be enabled for parts LPC1311/13/42/43.
• IRC status has no effect for parts LPC1311/01 and LPC1313/01.
Enabling sequence for UART clock
Requirements for enabling the UART peripheral clock:
• The UART pins must be configured in the IOCON block before the UART clock can be enabled
in the
in the SYSAHBCLKCTRL register (Table 25) for parts LPC1311/13/42/43.
• The sequence of configuring the UART pins and the UART clock has no effect for
parts LPC1311/01 and LPC1313/01.
3.2 Introduction
The system configuration block controls oscillators, the power management unit, and
clock generation of the LPC13xx. Also included in this block are registers for setting the
priority for AHB access and a register for remapping flash, SRAM, and ROM memory
areas.
LPC1300 LPC1343FHN33 4 (programmable) 1 (fixed)
LPC1300L LPC1311FHN33/01 4 (programmable) 4 (programmable)
LPC1300L LPC1313FHN33/01 4 (programmable) 4 (programmable)
LPC1300L LPC1313FBD48/01 4 (programmable) 4 (programmable)
Table 5. BOD interrupt and reset levels
Series Type number Interrupt levels Reset levels
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