NXP Semiconductors LPC1311 User Manual

UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 366 of 368
NXP Semiconductors
UM10375
Chapter 23: LPC13xx Supplementary information
15.8.5 Prescale Counter register (TMR16B0PC -
address 0x4000 C010 and TMR16B1PC -
address 0x4001 0010) . . . . . . . . . . . . . . . . . 271
15.8.6 Match Control Register (TMR16B0MCR and
TMR16B1MCR) . . . . . . . . . . . . . . . . . . . . . . 271
15.8.7 Match Registers (TMR16B0MR0/1/2/3 -
addresses 0x4000 C018/1C/20/24 and
TMR16B1MR0/1/2/3 - addresses 0x4001
0018/1C/20/24). . . . . . . . . . . . . . . . . . . . . . . 272
15.8.8 Capture Control Register (TMR16B0CCR and
TMR16B1CCR) . . . . . . . . . . . . . . . . . . . . . . 273
15.8.9 Capture Register (CT16B0CR0 - address 0x4000
C02C and CT16B1CR0 - address
0x4001 002C) . . . . . . . . . . . . . . . . . . . . . . . 273
15.8.10 External Match Register (TMR16B0EMR and
TMR16B1EMR) . . . . . . . . . . . . . . . . . . . . . . 274
15.8.11 Count Control Register (TMR16B0CTCR and
TMR16B1CTCR) . . . . . . . . . . . . . . . . . . . . . 275
15.8.12 PWM Control register (TMR16B0PWMC and
TMR16B1PWMC) . . . . . . . . . . . . . . . . . . . . 276
15.8.13 Rules for single edge controlled PWM
outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
15.9 Example timer operation . . . . . . . . . . . . . . . 278
15.10 Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . 279
Chapter 16: LPC13xx 32-bit timer/counters (CT32B0/1)
16.1 How to read this chapter. . . . . . . . . . . . . . . . 280
16.2 Basic configuration . . . . . . . . . . . . . . . . . . . . 280
16.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
16.4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 280
16.5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
16.6 Pin description. . . . . . . . . . . . . . . . . . . . . . . . 281
16.7 Clocking and power control . . . . . . . . . . . . . 281
16.8 Register description . . . . . . . . . . . . . . . . . . . 281
16.8.1 Interrupt Register (TMR32B0IR and
TMR32B1IR). . . . . . . . . . . . . . . . . . . . . . . . . 283
16.8.2 Timer Control Register (TMR32B0TCR and
TMR32B1TCR). . . . . . . . . . . . . . . . . . . . . . . 284
16.8.3 Timer Counter (TMR32B0TC - address
0x4001 4008 and TMR32B1TC - address
0x4001 8008) . . . . . . . . . . . . . . . . . . . . . . . . 284
16.8.4 Prescale Register (TMR32B0PR - address
0x4001 400C and TMR32B1PR - address
0x4001 800C). . . . . . . . . . . . . . . . . . . . . . . . 284
16.8.5 Prescale Counter Register (TMR32B0PC -
address 0x4001 4010 and TMR32B1PC - address
0x4001 8010) . . . . . . . . . . . . . . . . . . . . . . . . 285
16.8.6 Match Control Register (TMR32B0MCR and
TMR32B1MCR) . . . . . . . . . . . . . . . . . . . . . . 285
16.8.7 Match Registers (TMR32B0MR0/1/2/3 -
addresses 0x4001 4018/1C/20/24 and
TMR32B1MR0/1/2/3 addresses 0x4001
8018/1C/20/24) . . . . . . . . . . . . . . . . . . . . . . 286
16.8.8 Capture Control Register (TMR32B0CCR and
TMR32B1CCR) . . . . . . . . . . . . . . . . . . . . . . 287
16.8.9 Capture Register (TMR32B0CR0 - address
0x4001 402C and TMR32B1CR0 - address
0x4001 802C) . . . . . . . . . . . . . . . . . . . . . . . 287
16.8.10 External Match Register (TMR32B0EMR and
TMR32B1EMR) . . . . . . . . . . . . . . . . . . . . . . 287
16.8.11 Count Control Register (TMR32B0CTCR and
TMR32B1TCR) . . . . . . . . . . . . . . . . . . . . . . 289
16.8.12 PWM Control Register (TMR32B0PWMC and
TMR32B1PWMC) . . . . . . . . . . . . . . . . . . . . 290
16.8.13 Rules for single edge controlled PWM
outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
16.9 Example timer operation . . . . . . . . . . . . . . . 292
16.10 Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . 293
Chapter 17: LPC13xx System tick timer
17.1 How to read this chapter. . . . . . . . . . . . . . . . 294
17.2 Basic configuration . . . . . . . . . . . . . . . . . . . . 294
17.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
17.4 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
17.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
17.6 Register description . . . . . . . . . . . . . . . . . . . 295
17.6.1 System Timer Control and status register (CTRL -
0xE000 E010). . . . . . . . . . . . . . . . . . . . . . . . 296
17.6.2 System Timer Reload value register (LOAD -
0xE000 E014) . . . . . . . . . . . . . . . . . . . . . . . 296
17.6.3 System Timer Current value register (VAL -
0xE000 E018) . . . . . . . . . . . . . . . . . . . . . . . 296
17.6.4 System Timer Calibration value register (CALIB -
0xE000 E01C) . . . . . . . . . . . . . . . . . . . . . . . 297
17.7 Example timer calculations . . . . . . . . . . . . . 298
System clock = 72 MHz . . . . . . . . . . . . . . . . . 298
System tick timer clock = 24 MHz . . . . . . . . . 298
System clock = 12 MHz . . . . . . . . . . . . . . . . . 298
Chapter 18: LPC13xx WatchDog Timer (WDT)
18.1 How to read this chapter. . . . . . . . . . . . . . . . 299
18.2 Basic configuration . . . . . . . . . . . . . . . . . . . . 299
18.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
18.4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 299
18.5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . 300
18.6 Clocking and power control. . . . . . . . . . . . . 300
18.7 Register description . . . . . . . . . . . . . . . . . . . 301

NXP Semiconductors LPC1311 Specifications

General

Brand	NXP Semiconductors
Model	LPC1311
Category	Controller
Language	English