NXP Semiconductors LPC1311 User Manual

UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 353 of 368
NXP Semiconductors
UM10375
Chapter 23: LPC13xx Supplementary information
Table 50. Start logic reset register 1 (STARTRSRP1CLR,
address 0x4004 8218) bit description . . . . . . .37
Table 51. Start logic signal status register 1 (STARTSRP1,
address 0x4004 821C) bit description . . . . . .37
Table 52. Allowed values for PDSLEEPCFG register . . .37
Table 53. Deep-sleep configuration register
(PDSLEEPCFG, address 0x4004 8230) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Table 54. Wake-up configuration register (PDAWAKECFG,
address 0x4004 8234) bit description . . . . . . .38
Table 55. Power-down configuration register (PDRUNCFG,
address 0x4004 8238) bit description . . . . . . .40
Table 56. Device ID register (DEVICE_ID, address 0x4004
83F4) bit description. . . . . . . . . . . . . . . . . . . . .41
Table 57. PLL frequency parameters . . . . . . . . . . . . . . . .49
Table 58. PLL configuration examples . . . . . . . . . . . . . . .50
Table 59. Flash configuration register (FLASHCFG, address
0x4003 C010) bit description . . . . . . . . . . . . . .51
Table 60. Register overview: PMU (base address 0x4003
8000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Table 61. Power control register (PCON, address 0x4003
8000) bit description . . . . . . . . . . . . . . . . . . . .52
Table 62. General purpose registers 0 to 3 (GPREG0 -
GPREG3, address 0x4003 8004 to 0x4003 8010)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 63. General purpose register 4 (GPREG4, address
0x4003 8014) bit description . . . . . . . . . . . . .53
Table 64. set_pll routine . . . . . . . . . . . . . . . . . . . . . . . . .56
Table 65. set_power routine . . . . . . . . . . . . . . . . . . . . . .60
Table 66. Connection of interrupt sources to the Vectored
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . .63
Table 67. Register overview: NVIC (base address 0xE000
E000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Table 68. Interrupt Set-Enable Register 0 register (ISER0 -
address 0xE000 E100) bit description . . . . . .66
Table 69. Interrupt Set-Enable Register 1 register (ISER1 -
address 0xE000 E104) bit description . . . . . .67
Table 70. Interrupt Clear-Enable Register 0 . . . . . . . . . .68
Table 71. Interrupt Clear-Enable Register 1 register (ICER1
- address 0xE000 E184) bit description . . . . .69
Table 72. Interrupt Set-Pending Register 0 register (ISPR0 -
address 0xE000 E200) bit description . . . . . . .70
Table 73. Interrupt Set-Pending Register 1 register (ISPR1 -
address 0xE000 E204) bit description . . . . . . .72
Table 74. Interrupt Clear-Pending Register 0 register
(ICPR0 - address 0xE000 E280) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Table 75. Interrupt Set-Pending Register 1 register (ISPR1 -
address 0xE000 E204) bit description . . . . . . .74
Table 76. Interrupt Active Bit Register 0 (IABR0 - address
0xE000 E300) bit description . . . . . . . . . . . . . .75
Table 77. Interrupt Active Bit Register 1 (IABR1 - address
0xE000 E304) bit description . . . . . . . . . . . . . .76
Table 78. Interrupt Priority Register 0 (IPR0 - address
0xE000 E400) bit description . . . . . . . . . . . . . .77
Table 79. Interrupt Priority Register 1 (IPR1 - address
0xE000 E404) bit description . . . . . . . . . . . . . .77
Table 80. Interrupt Priority Register 2 (IPR2 - address
0xE000 E408) bit description. . . . . . . . . . . . . . 78
Table 81. Interrupt Priority Register 3 (IPR3 - address
0xE000 E40C) bit description . . . . . . . . . . . . . 78
Table 82. Interrupt Priority Register 4 (IPR4 - address
0xE000 E410) bit description. . . . . . . . . . . . . . 79
Table 83. Interrupt Priority Register 5 (IPR5 - address
0xE000 E414) bit description. . . . . . . . . . . . . . 79
Table 84. Interrupt Priority Register 60 (IPR6 - address
0xE000 E418) bit description. . . . . . . . . . . . . . 80
Table 85. Interrupt Priority Register 7 (IPR7 - address
0xE000 E41C) bit description . . . . . . . . . . . . . 80
Table 86. Interrupt Priority Register 8 (IPR8 - address
0xE000 E420) bit description. . . . . . . . . . . . . . 81
Table 87. Interrupt Priority Register 9 (IPR9 - address
0xE000 E424) bit description. . . . . . . . . . . . . . 81
Table 88. Interrupt Priority Register 10 (IPR10 - address
0xE000 E428) bit description. . . . . . . . . . . . . . 82
Table 89. Interrupt Priority Register 11 (IPR11 - address
0xE000 E42C) bit description . . . . . . . . . . . . . 82
Table 90. Interrupt Priority Register 12 (IPR12 - address
0xE000 E430) bit description. . . . . . . . . . . . . . 83
Table 91. Interrupt Priority Register 13 (IPR13 - address
0xE000 E434) bit description. . . . . . . . . . . . . . 83
Table 92. Interrupt Priority Register 14 (IPR14 - address
0xE000 E438) bit description. . . . . . . . . . . . . . 84
Table 93. Software Trigger Interrupt Register (STIR -
address 0xE000 EF00) bit description. . . . . . . 84
Table 94. Availability of IOCON registers. . . . . . . . . . . . . 85
Table 95. Register overview: I/O configuration block (base
address 0x4004 4000) . . . . . . . . . . . . . . . . . . 88
Table 96. I/O configuration registers ordered by port number
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 97. IOCON_PIO2_6 register (IOCON_PIO2_6,
address 0x4004 4000) bit description . . . . . . . 90
Table 98. IOCON_PIO2_0 register (IOCON_PIO2_0,
address 0x4004 4008) bit description . . . . . . 91
Table 99. IOCON_nRESET_PIO0_0 register
(IOCON_nRESET_PIO0_0, address 0x4004
400C) bit description . . . . . . . . . . . . . . . . . . . . 92
Table 100. IOCON_PIO0_1 register (IOCON_PIO0_1,
address 0x4004 4010) bit description . . . . . . . 92
Table 101. IOCON_PIO1_8 register (IOCON_PIO1_8,
address 0x4004 4014) bit description . . . . . . 93
Table 102. IOCON_PIO0_2 register (IOCON_PIO0_2,
address 0x4004 401C) bit description . . . . . . 93
Table 103. IOCON_PIO2_7 register (IOCON_PIO2_7,
address 0x4004 4020) bit description . . . . . . . 94
Table 104. IOCON_PIO2_8 register (IOCON_PIO2_8,
address 0x4004 4024) bit description . . . . . . . 95
Table 105. IOCON_PIO2_1 register (IOCON_PIO2_1,
address 0x4004 4028) bit description . . . . . . . 95
Table 106. IOCON_PIO0_3 register (IOCON_PIO0_3,
address 0x4004 402C) bit description . . . . . . 96
Table 107. IOCON_PIO0_4 register (IOCON_PIO0_4,
address 0x4004 4030) bit description . . . . . . 96
Table 108. IOCON_PIO0_5 register (IOCON_PIO0_5,
address 0x4004 4034) bit description . . . . . . . 97
Table 109. IOCON_PIO1_9 register (IOCON_PIO1_9,

NXP Semiconductors LPC1311 Specifications

General

Brand	NXP Semiconductors
Model	LPC1311
Category	Controller
Language	English