UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 31 of 368
NXP Semiconductors
UM10375
Chapter 3: LPC13xx System configuration
3.5.30 CLKOUT clock source select register
This register configures the clkout_clk signal to be output on the CLKOUT pin. All three
oscillators and the main clock can be selected for the clkout_clk clock.
The CLKOUTCLKUEN register (see Section 3.5.31
) must be toggled from LOW to HIGH
for the update to take effect.
Remark: When switching clock sources, both clocks must be running before the clock
source is updated.
3.5.31 CLKOUT clock source update enable register
This register updates the clock source of the CLKOUT pin with the new clock after the
CLKOUTCLKSEL register has been written to. In order for the update to take effect at the
input of the CLKOUT pin, first write a zero to the CLKCLKUEN register and then write a
one to CLKCLKUEN.
Remark: When switching clock sources, both clocks must be running before the clock
source is updated.
3.5.32 CLKOUT clock divider register
This register determines the divider value for the clkout_clk signal on the CLKOUT pin.
Table 37. CLKOUT clock source select register (CLKOUTCLKSEL, address 0x4004 80E0) bit
description
Bit Symbol Value Description Reset
value
1:0 SEL CLKOUT clock source 0x00
0x0 IRC oscillator
0x1 System oscillator
0x2 Watchdog oscillator
0x3 Main clock
31:2 - - Reserved 0x00
Table 38. CLKOUT clock source update enable register (CLKOUTUEN, address 0x4004
80E4) bit description
Bit Symbol Value Description Reset value
0 ENA Enable CLKOUT clock source update 0x0
0 No change
1 Update clock source
31:1 - - Reserved 0x00
To Next Page
Loading...
Need help?
General
