UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 85 of 368
7.1 How to read this chapter
The implementation of the I/O configuration registers varies for different LPC13xx parts
and packages. See Table 94
and Table 96 for IOCON registers and register bits which are
not used in all parts or packages.
For the LPC1311/01 and LPC1313/01, a pseudo open-drain mode can be selected in the
IOCON registers for each digital pins except the I2C pins. The open-drain mode is not
available in the LPC1311/13/42/43 parts.
[1] In registers IOCON_PIO0_1, IOCON_PIO0_3, IOCON_PIO0_6
[2] In registers IOCON_PIO2_0, IOCON_PIO2_1, IOCON_PIO2_2, IOCON_PIO2_3
[3] In registers IOCON_PIO3_0, IOCON_PIO3_1, IOCON_PIO3_2, IOCON_PIO3_3
[4] IOCON_DSR, IOCON_DCD, IOCON_RI registers
7.2 Introduction
The I/O configuration registers control the electrical characteristics of the pins. The
following characteristics are configurable:
• pin function
• internal pull-up/pull-down or Repeater mode function
• hysteresis
• analog input or digital mode for pins hosting the ADC inputs
• I
2
C mode for pins hosting the I
2
C-bus function
UM10375
Chapter 7: LPC13xx I/O configuration
Rev. 3 — 14 June 2011 User manual
Table 94. Availability of IOCON registers
Part IOCON_PIO2_1
to
IOCON_PIO2_11
IOCON_PIO3_0,
IOCON_PIO3_1,
IOCON_PIO3_3
IOCON_PIO3_4,
IOCON_PIO3_5
USB
function
[1]
SSP1
function
[2]
UART
additional
modem
function
[3]
UART
location
registers
[4]
LPC1311FHN33 no no yes no no no no
LPC1311FHN33/01 no no yes no no no no
LPC1313FHN33 no no yes no no no no
LPC1313FHN33/01 no no yes no no no no
LPC1313FBD48 yes yes yes no no no no
LPC1313FBD48/01 yes yes yes no yes yes yes
LPC1342FHN33 no no no yes no no no
LPC1342FBD48 yes yes no yes no no no
LPC1343FHN33 no no no yes no no no
LPC1343FBD48 yes yes no yes no no no
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