UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 55 of 368
NXP Semiconductors
UM10375
Chapter 5: LPC13xx Power profiles
5.4 Definitions
The following elements have to be defined in an application that uses the power profiles:
typedef struct _PWRD {
void (*set_pll)(unsigned int cmd[], unsigned int resp[]);
void (*set_power)(unsigned int cmd[], unsigned int resp[]);
} PWRD;
typedef struct _ROM {
const PWRD * pWRD;
} ROM;
ROM ** rom = (ROM **) 0x1FFF1FF8;
unsigned int command[4], result[2];
5.5 Clocking routine
5.5.1 set_pll
This routine sets up the system PLL according to the calling arguments. If the expected
clock can be obtained by simply dividing the system PLL input, set_pll bypasses the PLL
to lower system power consumption.
Remark: Before this routine is invoked, the PLL clock source (IRC/system oscillator) must
be selected (Table 18
), the main clock source must be set to the input clock to the system
PLL (Table 22
) and the system/AHB clock divider must be set to 1 (Table 24).
set_pll attempts to find a PLL setup that matches the calling parameters. Once a
combination of a feedback divider value (SYSPLLCTRL, M), a post divider ratio
(SYSPLLCTRL, P) and the system/AHB clock divider (SYSAHBCLKDIV) is found, set_pll
applies the selected values and switches the main clock source selection to the system
PLL clock out (if necessary).
Fig 7. LPC1311/01 and LPC1313/01 clock configuration for power API use
SYS PLL
irc_osc_clk
sys_osc_clk
irc_osc_clk
wdt_osc_clk
MAINCLKSEL
SYSPLLCLKSEL
CLOCK
DIVIDER
SYSAHBCLKCTRL[1]
(ROM enable)
SYSAHBCLKCTRL[18]
(SSP1 enable)
CLOCK
DIVIDER
Peripherals
main clock system clock
sys_pllclkin
sys_pllclkout
7
ARM
CORTEX-M3
ROM
SSP1
SYSAHBCLKDIV
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