NXP Semiconductors LPC1311 User Manual

UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 68 of 368
NXP Semiconductors
UM10375
Chapter 6: LPC13xx Interrupt controller
6.6.3 Interrupt Clear-Enable Register 0
The ICER0 register allows disabling the first 32 peripheral interrupts, or for reading the
enabled state of those interrupts. The remaining interrupts are disabled via the ICER1
register (Section 6.6.4
). Enabling interrupts is done through the ISER0 and ISER1
registers (Section 6.6.1
and Section 6.6.2).
The bit description is as follows for all bits in this register:
Write — Writing 0 has no effect, writing 1 disables the interrupt.
Read — 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
11 ISE_CT32B0 Timer CT32B0 interrupt enable.
12 ISE_CT32B1 Timer CT32B1 interrupt enable.
13 ISE_SSP0 SSP0 interrupt enable.
14 ISE_UART UART interrupt enable.
15 ISE_USBIRQ USB IRQ interrupt enable.
16 ISE_USBFRQ USB FRQ interrupt enable.
17 ISE_ADC ADC interrupt enable.
18 ISE_WDT WDT interrupt enable.
19 ISE_BOD BOD interrupt enable.
20 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
21 ISE_PIO_3 GPIO port 3 interrupt enable.
22 ISE_PIO_2 GPIO port 2 interrupt enable.
23 ISE_PIO_1 GPIO port 1 interrupt enable.
24 ISE_PIO_0 GPIO port 0 interrupt enable.
25 ISE_SSP1 SSP1 interrupt enable.
31:26 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Table 69. Interrupt Set-Enable Register 1 register (ISER1 - address 0xE000 E104) bit
description
…continued
Bit Symbol Description
Table 70. Interrupt Clear-Enable Register 0
Bit Symbol Description
0 ICE_PIO0_0 PIO0_0 start logic input interrupt disable.
1 ICE_PIO0_1 PIO0_1 start logic input interrupt disable.
2 ICE_PIO0_2 PIO0_2 start logic input interrupt disable.
3 ICE_PIO0_3 PIO0_3 start logic input interrupt disable.
4 ICE_PIO0_4 PIO0_4 start logic input interrupt disable.
5 ICE_PIO0_5 PIO0_5 start logic input interrupt disable.
6 ICE_PIO0_6 PIO0_6 start logic input interrupt disable.
7 ICE_PIO0_7 PIO0_7 start logic input interrupt disable.
8 ICE_PIO0_8 PIO0_8 start logic input interrupt disable.
9 ICE_PIO0_9 PIO0_9 start logic input interrupt disable.
10 ICE_PIO0_10 PIO0_10 start logic input interrupt disable.

NXP Semiconductors LPC1311 Specifications

General

Brand	NXP Semiconductors
Model	LPC1311
Category	Controller
Language	English