NXP Semiconductors LPC1311 User Manual

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User manual Rev. 3 — 14 June 2011 66 of 368
NXP Semiconductors
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Chapter 6: LPC13xx Interrupt controller
6.6.1 Interrupt Set-Enable Register 0 register
The ISER0 register allows enabling the first 32 peripheral interrupts, or for reading the
enabled state of those interrupts. The remaining interrupts are enabled via the ISER1
register (Section 6.6.2
). Disabling interrupts is done through the ICER0 and ICER1
registers (Section 6.6.3
and Section 6.6.4).
The bit description is as follows for all bits in this register:
Write — Writing 0 has no effect, writing 1 enables the interrupt.
Read — 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
IPR9 RW 0x424 Interrupt Priority Registers 9 This register allows assigning a priority to each
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
0
IPR10 RW 0x428 Interrupt Priority Registers 10 This register allows assigning a priority to each
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
0
IPR11 RW 0x42C Interrupt Priority Registers 11 This register allows assigning a priority to each
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
0
IPR12 RW 0x430 Interrupt Priority Registers 12 This register allows assigning a priority to each
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
0
IPR13 RW 0x434 Interrupt Priority Registers 13 This register allows assigning a priority to each
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
0
IPR14 RW 0x438 Interrupt Priority Registers 14 This register allows assigning a priority to each
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
0
STIR WO 0xF00 Software Trigger Interrupt Register. This register allows software to generate an
interrupt.
0
Table 67. Register overview: NVIC (base address 0xE000 E000)
…continued
Name Access Address
offset
Description Reset
value
Table 68. Interrupt Set-Enable Register 0 register (ISER0 - address 0xE000 E100) bit
description
Bit Symbol Description
0 ISE_PIO0_0 PIO0_0 start logic input interrupt enable.
1 ISE_PIO0_1 PIO0_1 start logic input interrupt enable.
2 ISE_PIO0_2 PIO0_2 start logic input interrupt enable.
3 ISE_PIO0_3 PIO0_3 start logic input interrupt enable.
4 ISE_PIO0_4 PIO0_4 start logic input interrupt enable.
5 ISE_PIO0_5 PIO0_5 start logic input interrupt enable.
6 ISE_PIO0_6 PIO0_6 start logic input interrupt enable.
7 ISE_PIO0_7 PIO0_7 start logic input interrupt enable.
8 ISE_PIO0_8 PIO0_8 start logic input interrupt enable.
9 ISE_PIO0_9 PIO0_9 start logic input interrupt enable.
10 ISE_PIO0_10 PIO0_10 start logic input interrupt enable.
11 ISE_PIO0_11 PIO0_11 start logic input interrupt enable.
12 ISE_PIO1_0 PIO1_0 start logic input interrupt enable.
13 ISE_PIO1_1 PIO1_1 start logic input interrupt enable.
14 ISE_PIO1_2 PIO1_2 start logic input interrupt enable.

NXP Semiconductors LPC1311 Specifications

General

Brand	NXP Semiconductors
Model	LPC1311
Category	Controller
Language	English