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User manual Rev. 3 — 14 June 2011 79 of 368
NXP Semiconductors
UM10375
Chapter 6: LPC13xx Interrupt controller
6.6.15 Interrupt Priority Register 4
The IPR4 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 32 priorities, where 0 is the highest priority.
6.6.16 Interrupt Priority Register 5
The IPR5 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 32 priorities, where 0 is the highest priority.
Table 82. Interrupt Priority Register 4 (IPR4 - address 0xE000 E410) bit description
Bit Symbol Description
4:0 Unimplemented These bits ignore writes, and read as 0.
7:5 IP_PIO1_4 PIO0_4 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
12:8 Unimplemented These bits ignore writes, and read as 0.
15:13 IP_PIO1_5 PIO0_5 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
20:16 Unimplemented These bits ignore writes, and read as 0.
23:21 IP_PIO1_6 PIO0_6 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
28:24 Unimplemented These bits ignore writes, and read as 0.
31:29 IP_PIO1_7 PIO0_7 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
Table 83. Interrupt Priority Register 5 (IPR5 - address 0xE000 E414) bit description
Bit Symbol Description
4:0 Unimplemented These bits ignore writes, and read as 0.
7:5 IP_PIO1_8 PIO1_8 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
12:8 Unimplemented These bits ignore writes, and read as 0.
15:13 IP_PIO1_9 PIO1_9 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
20:16 Unimplemented These bits ignore writes, and read as 0.
23:21 IP_PIO1_10 PIO1_10 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest
priority.
28:24 Unimplemented These bits ignore writes, and read as 0.
31:29 IP_PIO1_11 PIO1_11 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest
priority.
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