NXP Semiconductors LPC1311 User Manual

UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 131 of 368
NXP Semiconductors
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Chapter 9: LPC13xx General Purpose I/O (GPIO)
9.4 Register description
Each GPIO register can be up to 12 bits wide and can be read or written using word or
half-word operations at word addresses.
9.4.1 GPIO data register
The GPIODATA register holds the current state of the pin (HIGH or LOW), independently
of whether the pin is configured as an GPIO input or output or as another digital function.
If the pin is configured as GPIO output, the current value of the GPIODATA register is
driven to the pin.
A read of the GPIODATA register always returns the current logic level (state) of the pin
independently of its configuration. Because there is a single data register for both the
value of the output driver and the state of the pin’s input, write operations have different
effects depending on the pin’s configuration:
• If a pin is configured as GPIO input, a write to the GPIODATA register has no effect on
the pin level. A read returns the current state of the pin.
Table 148. Register overview: GPIO (base address port 0: 0x5000 0000; port 1: 0x5001 0000, port 2: 0x5002 0000;
port 3: 0x5003 0000)
Name Access Address offset Description Reset
value
GPIODATAMASK R/W 0x0000 to 0x3FF8 Port n data address masking register
locations for pins PIOn_0 to PIOn_11 (see
Section 9.5.1
)
n/a
GPIODATA R/W 0x3FFC Port n data register for pins PIOn_0 to
PIOn_11
n/a
- - 0x4000 to 0x7FFC Reserved -
GPIODIR R/W 0x8000 Data direction register for port n 0x00
GPIOIS R/W 0x8004 Interrupt sense register for port n 0x00
GPIOIBE R/W 0x8008 Interrupt both edges register for port n 0x00
GPIOIEV R/W 0x800C Interrupt event register for port n 0x00
GPIOIE R/W 0x8010 Interrupt mask register for port n 0x00
GPIORIS R 0x8014 Raw interrupt status register for port n 0x00
GPIOMIS R 0x8018 Masked interrupt status register for port n 0x00
GPIOIC W 0x801C Interrupt clear register for port n 0x00
- - 0x8020 - 0xFFFF Reserved 0x00
Table 149. GPIO data register (GPIO0DATA, address 0x5000 3FFC; GPIO1DATA, address
0x5001 3FFC; GPIO2DATA, address 0x5002 3FFC; GPIO3DATA, address 0x5003
3FFC) bit description
Bit Symbol Description Reset
value
Access
11:0 DATA Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW =
0.
n/a R/W
31:12 - Reserved 0x00 -

NXP Semiconductors LPC1311 Specifications

General

Brand	NXP Semiconductors
Model	LPC1311
Category	Controller
Language	English