UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 313 of 368
NXP Semiconductors
UM10375
Chapter 20: LPC13xx Analog-to-Digital Converter (ADC)
20.5 Clocking and power control
The peripheral clock to the ADC (PCLK) is provided by the system clock (see Figure 3).
This clock can be disabled through bit 13 in the SYSAHBCLKCTRL register (Table 25
) for
power savings.
The ADC can be powered down at run-time using the PDRUNCFG register (Table 55
).
Basic clocking for the A/D converters is determined by the peripheral ADC clock PCLK. A
programmable divider is included in each converter to scale this clock to the 4.5 MHz
(max) clock needed by the successive approximation process. An accurate conversion
requires 11 clock cycles.
20.6 Register description
The ADC contains registers organized as shown in Table 304.
[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
Table 304. Register overview: ADC (base address 0x4001 C000)
Name Access Address
offset
Description Reset
Value
[1]
AD0CR R/W 0x000 A/D Control Register. The AD0CR register must be written to select the
operating mode before A/D conversion can occur.
0x0000 0000
AD0GDR R/W 0x004 A/D Global Data Register. Contains the result of the most recent A/D
conversion.
NA
- - 0x008 Reserved. -
AD0INTEN R/W 0x00C A/D Interrupt Enable Register. This register contains enable bits that allow
the DONE flag of each A/D channel to be included or excluded from
contributing to the generation of an A/D interrupt.
0x0000 0100
AD0DR0 R/W 0x010 A/D Channel 0 Data Register. This register contains the result of the most
recent conversion completed on channel 0
NA
AD0DR1 R/W 0x014 A/D Channel 1 Data Register. This register contains the result of the most
recent conversion completed on channel 1.
NA
AD0DR2 R/W 0x018 A/D Channel 2 Data Register. This register contains the result of the most
recent conversion completed on channel 2.
NA
AD0DR3 R/W 0x01C A/D Channel 3 Data Register. This register contains the result of the most
recent conversion completed on channel 3.
NA
AD0DR4 R/W 0x020 A/D Channel 4 Data Register. This register contains the result of the most
recent conversion completed on channel 4.
NA
AD0DR5 R/W 0x024 A/D Channel 5 Data Register. This register contains the result of the most
recent conversion completed on channel 5.
NA
AD0DR6 R/W 0x028 A/D Channel 6 Data Register. This register contains the result of the most
recent conversion completed on channel 6.
NA
AD0DR7 R/W 0x02C A/D Channel 7 Data Register. This register contains the result of the most
recent conversion completed on channel 7.
NA
AD0STAT RO 0x030 A/D Status Register. This register contains DONE and OVERRUN flags for
all of the A/D channels, as well as the A/D interrupt flag.
0
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