NXP Semiconductors LPC1311 User Manual

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User manual Rev. 3 — 14 June 2011 352 of 368
NXP Semiconductors
UM10375
Chapter 23: LPC13xx Supplementary information
23.3 Tables
Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .5
Table 2. Ordering options for LPC13xx . . . . . . . . . . . . . .5
Table 3. LPC13xx memory configuration . . . . . . . . . . . . .8
Table 4. USB related registers and register bits reserved
for LPC1311/13. . . . . . . . . . . . . . . . . . . . . . . . .10
Table 5. BOD interrupt and reset levels . . . . . . . . . . . . .10
Table 6. Pin summary. . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 7. Register overview: system control block (base
address 0x4004 8000) . . . . . . . . . . . . . . . . . .15
Table 8. System memory remap register
(SYSMEMREMAP, address 0x4004 8000) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 9. Peripheral reset control register (PRESETCTRL,
address 0x4004 8004) bit description. . . . . . . .17
Table 10. System PLL control register (SYSPLLCTRL,
address 0x4004 8008) bit description . . . . . . .18
Table 11. System PLL status register (SYSPLLSTAT,
address 0x4004 800C) bit description . . . . . . .18
Table 12. USB PLL control register (USBPLLCTRL, address
0x4004 8010) bit description . . . . . . . . . . . . . .18
Table 13. USB PLL status register (USBPLLSTAT, address
0x4004 8014) bit description . . . . . . . . . . . . . .19
Table 14. System oscillator control register (SYSOSCCTRL,
address 0x4004 8020) bit description. . . . . . . .20
Table 15. Watchdog oscillator control register
(WDTOSCCTRL, address 0x4004 8024) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 16. Internal resonant crystal control register
(IRCCTRL, address 0x4004 8028) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 17. System reset status register (SYSRESSTAT,
address 0x4004 8030) bit description. . . . . . . .22
Table 18. System PLL clock source select register
(SYSPLLCLKSEL, address 0x4004 8040) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 19. System PLL clock source update enable register
(SYSPLLCLKUEN, address 0x4004 8044) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 20. USB PLL clock source select register
(USBPLLCLKSEL, address 0x4004 8048) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 21. USB PLL clock source update enable register
(USBPLLCLKUEN, address 0x4004 804C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 22. Main clock source select register (MAINCLKSEL,
address 0x4004 8070) bit description. . . . . . . .24
Table 23. Main clock source update enable register
(MAINCLKUEN, address 0x4004 8074) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 24. System AHB clock divider register
(SYSAHBCLKDIV, address 0x4004 8078) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 25. System AHB clock control register
(SYSAHBCLKCTRL, address 0x4004 8080) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 26. SSP0 clock divider register (SSP0CLKDIV,
address 0x4004 8094) bit description . . . . . . . 27
Table 27. UART clock divider register (UARTCLKDIV,
address 0x4004 8098) bit description . . . . . . . 27
Table 28. SSP1 clock divider register (SSP1CLKDIV,
address 0x4004 809C) bit description . . . . . . . 28
Table 29. TRACECLKDIV clock divider register
(TRACECLKDIV, address 0x4004 80AC) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 30. SYSTICK clock divider register
(SYSTICKCLKDIV, address 0x4004 80B0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 31. USB clock source select register (USBCLKSEL,
address 0x4004 80C0) bit description . . . . . . . 29
Table 32. USB clock source update enable register
(USBCLKUEN, address 0x4004 80C4) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 33. USB clock divider register (USBCLKDIV, address
0x4004 80C8) bit description . . . . . . . . . . . . . . 29
Table 34. WDT clock source select register (WDTCLKSEL,
address 0x4004 80D0) bit description . . . . . . . 30
Table 35. WDT clock source update enable register
(WDTCLKUEN, address 0x4004 80D4) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 36. WDT clock divider register (WDTCLKDIV, address
0x4004 80D8) bit description . . . . . . . . . . . . . . 30
Table 37. CLKOUT clock source select register
(CLKOUTCLKSEL, address 0x4004 80E0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 38. CLKOUT clock source update enable register
(CLKOUTUEN, address 0x4004 80E4) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 39. CLKOUT clock divider registers (CLKOUTDIV,
address 0x4004 80E8) bit description . . . . . . . 32
Table 40. POR captured PIO status registers 0
(PIOPORCAP0, address 0x4004 8100) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 41. POR captured PIO status registers 1
(PIOPORCAP1, address 0x4004 8104) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 42. BOD control register (BODCTRL, address 0x4004
8150) bit description. . . . . . . . . . . . . . . . . . . . . 33
Table 43. System tick timer calibration register
(SYSTCKCAL, address 0x4004 8154) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 44. Start logic edge control register 0 (STARTAPRP0,
address 0x4004 8200) bit description . . . . . . 34
Table 45. Start logic signal enable register 0 (STARTERP0,
address 0x4004 8204) bit description . . . . . . 34
Table 46. Start logic reset register 0 (STARTRSRP0CLR,
address 0x4004 8208) bit description . . . . . . 35
Table 47. Start logic status register 0 (STARTSRP0,
address 0x4004 820C) bit description . . . . . . 35
Table 48. Start logic edge control register 1 (STARTAPRP1,
address 0x4004 8210) bit description . . . . . . 36
Table 49. Start logic signal enable register 1 (STARTERP1,
address 0x4004 8214) bit description . . . . . . 36

NXP Semiconductors LPC1311 Specifications

General

Brand	NXP Semiconductors
Model	LPC1311
Category	Controller
Language	English