UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 280 of 368
16.1 How to read this chapter
The 32-bit timer blocks are identical for all LPC13xx parts.
16.2 Basic configuration
The CT32B0/1 are configured using the following registers:
1. Pins: The CT32B0/1 pins must be configured in the IOCONFIG register block
(Section 7.4
).
2. Power and peripheral clock: In the SYSAHBCLKCTRL register, set bit 9 and bit 10
(Table 25
).
16.3 Features
• Two 32-bit counter/timers with a programmable 32-bit prescaler.
• Counter or Timer operation.
• One 32-bit capture channel that can take a snapshot of the timer value when an input
signal transitions. A capture event may also optionally generate an interrupt.
• Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Four external outputs corresponding to match registers with the following capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
• For each timer, up to four match registers can be configured as PWM allowing to use
up to three match outputs as single edge controlled PWM outputs.
16.4 Applications
• Interval timer for counting internal events
• Pulse Width Demodulator via capture input
• Free running timer
• Pulse Width Modulator via match outputs
UM10375
Chapter 16: LPC13xx 32-bit timer/counters (CT32B0/1)
Rev. 3 — 14 June 2011 User manual
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