UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 254 of 368
NXP Semiconductors
UM10375
Chapter 14: LPC13xx SSP0/1
14.7.1 SSP Control Register 0
This register controls the basic operation of the SSP controller.
14.7.2 SSP Control Register 1
This register controls certain aspects of the operation of the SSP controller.
Table 243: SSP Control Register 0 (SSP0CR0 - address 0x4004 0000, SSP1CR0 - address
0x4005 8000) bit description
Bit Symbol Value Description Reset
value
3:0 DSS Data Size Select. This field controls the number of bits
transferred in each frame. Values 0000-0010 are not
supported and should not be used.
0000
0x3 4-bit transfer
0x4 5-bit transfer
0x5 6-bit transfer
0x6 7-bit transfer
0x7 8-bit transfer
0x8 9-bit transfer
0x9 10-bit transfer
0xA 11-bit transfer
0xB 12-bit transfer
0xC 13-bit transfer
0xD 14-bit transfer
0xE 15-bit transfer
0xF 16-bit transfer
5:4 FRF Frame Format. 00
0x0 SPI
0x1 TI
0x2 Microwire
0x3 This combination is not supported and should not be used.
6 CPOL Clock Out Polarity. This bit is only used in SPI mode. 0
0 SSP controller maintains the bus clock low between frames.
1 SSP controller maintains the bus clock high between frames.
7 CPHA Clock Out Phase. This bit is only used in SPI mode. 0
0 SSP controller captures serial data on the first clock transition
of the frame, that is, the transition away from the inter-frame
state of the clock line.
1 SSP controller captures serial data on the second clock
transition of the frame, that is, the transition back to the
inter-frame state of the clock line.
15:8 SCR Serial Clock Rate. The number of prescaler-output clocks per
bit on the bus, minus one. Given that CPSDVSR is the
prescale divider, and the APB clock PCLK clocks the
prescaler, the bit frequency is PCLK / (CPSDVSR ï‚´ [SCR+1]).
0x00
31:16 - - Reserved. -
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