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User manual Rev. 3 — 14 June 2011 78 of 368
NXP Semiconductors
UM10375
Chapter 6: LPC13xx Interrupt controller
6.6.13 Interrupt Priority Register 2
The IPR2 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 32 priorities, where 0 is the highest priority.
6.6.14 Interrupt Priority Register 3
The IPR3 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 32 priorities, where 0 is the highest priority.
Table 80. Interrupt Priority Register 2 (IPR2 - address 0xE000 E408) bit description
Bit Symbol Description
4:0 Unimplemented These bits ignore writes, and read as 0.
7:5 IP_PIO0_8 PIO0_8 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
12:8 Unimplemented These bits ignore writes, and read as 0.
15:13 IP_PIO0_9 PIO0_9 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
20:16 Unimplemented These bits ignore writes, and read as 0.
23:21 IP_PIO0_10 PIO0_10 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest
priority.
28:24 Unimplemented These bits ignore writes, and read as 0.
31:29 IP_PIO0_11 PIO0_11 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest
priority.
Table 81. Interrupt Priority Register 3 (IPR3 - address 0xE000 E40C) bit description
Bit Symbol Description
4:0 Unimplemented These bits ignore writes, and read as 0.
7:5 IP_PIO1_0 PIO1_0 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
12:8 Unimplemented These bits ignore writes, and read as 0.
15:13 IP_PIO1_1 PIO1_1 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
20:16 Unimplemented These bits ignore writes, and read as 0.
23:21 IP_PIO1_2 PIO1_2 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
28:24 Unimplemented These bits ignore writes, and read as 0.
31:29 IP_PIO1_3 PIO1_3 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.