UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 358 of 368
NXP Semiconductors
UM10375
Chapter 23: LPC13xx Supplementary information
Table 340. IAP Read Boot Code version number
command . . . . . . . . . . . . . . . . . . . . . . . . . . . .340
Table 341. IAP Compare command. . . . . . . . . . . . . . . . .340
Table 342. Reinvoke ISP. . . . . . . . . . . . . . . . . . . . . . . . .340
Table 343. IAP ReadUID command. . . . . . . . . . . . . . . . .341
Table 344. IAP Status Codes Summary . . . . . . . . . . . . .341
Table 345. Memory mapping in debug mode . . . . . . . . .342
Table 346. Register overview: FMC (base address 0x4003
C000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .342
Table 347. Flash configuration register (FLASHCFG,
address 0x4003 C010) bit description . . . . . .343
Table 348. Flash Module Signature Start register
(FMSSTART - 0x4003 C020) bit description .343
Table 349. Flash Module Signature Stop register (FMSSTOP
- 0x4003 C024) bit description . . . . . . . . . . . .343
Table 350. FMSW0 register bit description (FMSW0,
address: 0x4003 C02C) . . . . . . . . . . . . . . . . .344
Table 351. FMSW1 register bit description (FMSW1,
address: 0x4003 C030) . . . . . . . . . . . . . . . . .344
Table 352. FMSW2 register bit description (FMSW2,
address: 0x4003 C034) . . . . . . . . . . . . . . . . .344
Table 353. FMSW3 register bit description (FMSW3,
address: 0x4003 40C8) . . . . . . . . . . . . . . . .344
Table 354. Flash module Status register (FMSTAT - 0x4003
CFE0) bit description . . . . . . . . . . . . . . . . . . .344
Table 355. Flash Module Status Clear register (FMSTATCLR
- 0x0x4003 CFE8) bit description . . . . . . . . . .345
Table 356. Serial Wire Debug pin description . . . . . . . . .348
Table 357. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . .350
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