NXP Semiconductors LPC1311 User Manual

UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 46 of 368
NXP Semiconductors
UM10375
Chapter 3: LPC13xx System configuration
3.9.4.2 Programming Deep power-down mode
The following steps must be performed to enter Deep power-down mode:
1. Write one to the DPDEN bit in the PCON register (see Table 61
).
2. Store data to be retained in the general purpose registers (Table 62
).
3. Write one to the SLEEPDEEP bit in the ARM Cortex-M3 SCR register.
4. For the LPC1311/13/42/43, ensure that the IRC is powered by setting bits
IRCOUT_PD and IRC_PD to zero in the PDRUNCFG register before entering Deep
power-down mode. This step is not required for the LPC1311/01 and LPC1313/01.
5. Use the ARM WFI instruction.
Remark: The WAKEUP pin must be pulled HIGH externally before entering Deep
power-down mode.
3.9.4.3 Wake-up from Deep power-down mode
Pulling the WAKEUP pin LOW wakes up the LPC13xx from Deep power-down, and the
chip goes through the entire reset process (Section 3.6
). The minimum pulse width for the
HIGH-to-LOW transition on the WAKEUP pin is 50 ns.
1. A wake-up signal is generated when a HIGH-to-LOW transition occurs externally on
the WAKEUP pin with a pulse length of at least 50 ns while the part is in Deep
power-down mode.
– The PMU will turn on the on-chip voltage regulator. When the core voltage reaches
the power-on-reset (POR) trip point, a system reset will be triggered and the chip
re-boots.
– All registers except the GPREG0 to GPREG4 will be in their reset state.
2. Once the chip has booted, read the deep power-down flag in the PCON register
(Table 61
) to verify that the reset was caused by a wake-up event from Deep
power-down.
3. Clear the deep power-down flag in the PCON register (Table 61
).
4. (Optional) Read the stored data in the general purpose registers (Table 62
and
Table 63
).
5. Set up the PMU for the next Deep power-down cycle.
Remark: The RESET
pin has no functionality in Deep power-down mode.
3.10 Deep-sleep mode details
3.10.1 IRC oscillator
The IRC is the only oscillator on the LPC13xx that can always shut down glitch-free.
Therefore it is recommended that the user switches the clock source to IRC before the
chip enters Deep-sleep mode.

NXP Semiconductors LPC1311 Specifications

General

Brand	NXP Semiconductors
Model	LPC1311
Category	Controller
Language	English