UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 65 of 368
NXP Semiconductors
UM10375
Chapter 6: LPC13xx Interrupt controller
6.6 Register description
The following table summarizes the registers in the NVIC as implemented in the LPC13xx.
The Cortex-M3 User Guide provides a functional description of the NVIC.
Table 67. Register overview: NVIC (base address 0xE000 E000)
Name Access Address
offset
Description Reset
value
ISER0 RW 0x100 Interrupt Set-Enable Register 0. This register allows enabling interrupts and
reading back the interrupt enables for specific peripheral functions.
0
ISER1 RW 0x104 Interrupt Set-Enable Register 1. This register allows enabling interrupts and
reading back the interrupt enables for specific peripheral functions.
0
ICER0 RW 0x180 Interrupt Clear-Enable Register 0. This register allows disabling interrupts and
reading back the interrupt enables for specific peripheral functions.
0
ICER1 RW 0x184 Interrupt Clear-Enable Register 1. This register allows disabling interrupts and
reading back the interrupt enables for specific peripheral functions.
0
ISPR0 RW 0x200 Interrupt Set-Pending Register 0. This register allows changing the interrupt
state to pending and reading back the interrupt pending state for specific
peripheral functions.
0
ISPR1 RW 0x204 Interrupt Set-Pending Register 1. This register allows changing the interrupt
state to pending and reading back the interrupt pending state for specific
peripheral functions.
0
ICPR0 RW 0x280 Interrupt Clear-Pending Register 0. This register allows changing the interrupt
state to not pending and reading back the interrupt pending state for specific
peripheral functions.
0
ICPR1 RW 0x284 Interrupt Clear-Pending Register 1. This register allows changing the interrupt
state to not pending and reading back the interrupt pending state for specific
peripheral functions.
0
IABR0 RO 0x300 Interrupt Active Bit Register 0. This register allows reading the current interrupt
active state for specific peripheral functions.
0
IABR1 RO 0x304 Interrupt Active Bit Register 1. This register allows reading the current interrupt
active state for specific peripheral functions.
0
IPR0 RW 0x400 Interrupt Priority Registers 0. This register allows assigning a priority to each
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
0
IPR1 RW 0x404 Interrupt Priority Registers 1 This register allows assigning a priority to each
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
0
IPR2 RW 0x408 Interrupt Priority Registers 2. This register allows assigning a priority to each
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
0
IPR3 RW 0x40C Interrupt Priority Registers 3. This register allows assigning a priority to each
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
0
IPR4 RW 0x410 Interrupt Priority Registers 4. This register allows assigning a priority to each
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
0
IPR5 RW 0x414 Interrupt Priority Registers 5. This register allows assigning a priority to each
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
0
IPR6 RW 0x418 Interrupt Priority Registers 6. This register allows assigning a priority to each
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
0
IPR7 RW 0x41C Interrupt Priority Registers 7. This register allows assigning a priority to each
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
0
IPR8 RW 0x420 Interrupt Priority Registers 8 This register allows assigning a priority to each
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
0
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